Ultra Low Power Memory Reliability Circuits for Error Detection and Correction

Abstract

 Past 20 years there has been significant change in Integrated Circuit Design and their fabrication. Due to portable devices which are operated using batteries, Transistors are scaled down to nanometer technology. As shrinkage continues in the field of CMOS VLSI Devices are more vulnerable for errors while transmitting data using chips i.e. communication between chips. This paper presents the basic theory behind identifying and fixing errors and provide some redundancy to the message so the receiver will use to check the message's accuracy and delete any compromised details. A scheme for detecting errors may be systemic or non-systematic: The sender sends specific data and a series of control bits in a systematic format comprising data bits, it is derived from a unique algorithm. If only error detection is needed, the receiver will use the same algorithm that was used to obtain the data bits and compare the results to the obtained control bits. If the values do not fit, an error may arise anywhere in the transmission path.